Memory system using non-distributed command/address clock

ABSTRACT

The present invention generally relates to memory system wherein clocks for sampling command and address signals are removed. The memory system comprising a plurality of memory devices includes: a controller for outputting a first clock signal, a second signal and a plurality of command/address input signals corresponding to the plurality of memory devices, respectively; and a register and delay circuit unit for outputting command/address output signals after receiving the command/address input signals from the controller and then correcting transmission delay due to transmission lines; wherein the plurality of memory devices receive the circuit unit via the transmission lines, respectively, and simple the command/address output signals using the first clock signal directly inputted from the controller. As a result, the memory system according to the present invention can simplify the layout of semiconductor device design and prevent the collision of clocks.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to memory systemscomprising a plurality of memory devices, and more particularly, to amemory system wherein a command/address clock ‘CACLK’ for samplingcommand/address signals is removed.

[0003] 2. Description of the Prior Art

[0004] A clock control device of conventional memory devices comprises aregister chip for buffering command/address input signals and a phaselocked loop ‘PLL’ chip for generating timing signals, in case of dual inline memory module ‘DIMM’. When a plurality of PLL output clocks aregenerated, a compensation capacitor (hereinafter, referred to as‘C_(comp)’) is used to control their edge timing.

[0005]FIG. 3 is a diagram illustrating an example of a conventionalmemory system using distributed command/address signals. A PLL circuit20 performs edge-controlling command/address clocks ‘CACLK’ inputtedfrom a controller 10 by using the C_(comp) in consideration of signaldelay generated from transmission lines, and adjusts the edge-controlledCACLKs to have the same phase with the CACLKs inputted in the controller10, and then applies the adjusted CACLKs, CLK0, CLK1, CLK2 and CLK3, toa plurality of memory devices 61, 62, 63 and 64, respectively. Here, aplurality of command/address input signals ‘CAin’ outputted from thecontroller 10 are outputted into the plurality of memory devices 61, 62,63 and 64, respectively, via transmission lines for distributing CACLKsand separate transmission lines after buffered in a register 30.

[0006] However, the conventional memory system has the followingproblems. First, the lay-out of semiconductor device design becomescomplicated because the conventional memory system should comprise CACLKtransmission lines corresponding to the number of a plurality of memorydevices for transmitting command/address signals and separatecommand/address clocks into memory devices, respectively. Second, clockdomain collision can be generated between command/address clocks andwrite data capture clocks because the memory devices receivecommand/address clocks and separate write data capture clocks ‘WCLK’.Third, each memory device should comprise an individual PLL or DLLcircuit, thereby increasing jitter as well as cost of the whole system.Fourth, because a register and a PLL circuit should be embodied usingseparate chips, fabrication of two chip packages makes the process ofsemiconductor devices complicated, thereby increasing the cost. Finally,timing margins are degraded due to differences of a plurality ofcompensation capacitors.

SUMMARY OF THE INVENTION

[0007] In order to overcome the above described problems, the presentinvention has an object to provide a memory system which simplifies thelay-out of semiconductor device design by removing transmission linesfor distributing command/address clocks CACLK, prevents clock domaincollision by sampling command/address signals according to write datacapture clocks WCLKs or clock signals divided into integer multiple,reduces cost without requiring an individual PLL or DLL circuit,improves jitter performance and prevents degradation of timing marginsof system due to differences of compensation capacitor.

[0008] A preferred embodiment of the present invention has an object toprovide a memory system for reducing cost due to unification of registerchip, PLL or DLL chips.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is block diagram of a memory system in accordance with apreferred embodiment of the present invention.

[0010]FIG. 2 is a detail diagram of a register and delay-circuit inaccordance with a preferred embodiment of the present invention.

[0011]FIG. 3 is a block diagram of a conventional memory system usingdistributed command/address clock.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] A disclosed memory system comprising a plurality of memorydevices includes: a controller for outputting a first clock signal, asecond clock signal and a plurality of command/address input signalscorresponding to the plurality of memory devices, respectively; and aregister and delay circuit unit for outputting command/address outputsignals after receiving the command/address input signals from thecontroller and then correcting transmission delay due to transmissionlines; wherein the plurality of memory devices receive thecommand/address output signal from the register and delay circuit unitvia the transmission lines, respectively, and sample the command/addressoutput signals using the first clock signal directly inputted from thecontroller.

[0013] The disclosed memory system comprising a plurality of memorydevices will be described in more details referring to examples below,when are not intended to be limiting.

[0014]FIG. 1 is block diagram of a memory system in accordance with apreferred embodiment of the present invention. As shown in FIG. 1, acontroller 10 for controlling the whole operation of memory systemapplies command/address input signals CAin to a register and delaycircuit unit 40.

[0015] The register and delay circuit unit 40 receiving thecommand/address input signals CAin outputs command/address outputsignals CAout after correcting transmission delay due to transmissionlines connected to memory devices 61, 62, 63 and 64 and transmissiondelay generated from internal output buffer. It is preferable that thetransmission delay means transmission delay ranging from a point (A)originated from the register and delay circuit 40 to a predeterminedpoint (B) in each of a plurality of transmission lines. The internaltransmission delay may also include transmission delay generated fromthe internal register and delay circuit unit of command/address signalsCAin. The plurality of memory devices 61, 62, 63 and 64 receivecommand/address output signals CAout outputted from the register anddelay circuit unit 40 via transmission lines, and then sample thereceived CAouts using write data clock (hereinafter, a first clocksignal:WCLK) directly inputted from the controller 10. Accordingly,because of not using a separate command/address clock signals, thememory system of the present invention does not require separatetransmission lines for command/address clock signals like theconventional memory system. Additionally, the collision are notgenerated between clock domains because a number of clocks are notinputted in memory devices but command/address signals CAout are sampledusing only WCLK.

[0016]FIG. 2 is a detail diagram of a register and delay circuit inaccordance with a preferred embodiment of the present invention.

[0017] A register unit 30 outputs command/address output signalsCAout_I˜CAout_j by sampling command/address input signals CAin_I˜CAin_jusing internal clock (hereinafter, referred to as a third clocksignal:intCLK). Here, a clock control circuit 41 generates a third clocksignal after correcting transmission delay due to transmission lines ofcommand/address clock (hereinafter, referred to as a second clocksignal:CACLK) inputted from the controller 10 and transmission delaygenerated from internal output buffer. It is preferable that thetransmission delay means transmission delay ranging from a point (A)originated from the register and delay circuit 40 to a predeterminedpoint (B). The internal output buffer transmission delay may alsoinclude transmission delay ranging from an output buffer input point (C)in the register and delay circuit unit 40 of command/address signal toan output point (D).

[0018] Preferably, as shown in FIG. 2, the clock control circuit 41comprises a DLL circuit 42, a first replica circuit 44 for modelingtransmission delay due to transmission lines and a second replicacircuit 43 for modeling transmission delay of internal output buffer.The DLL circuit 42 receives a second clock CACLK from the controller 10,and re-receives a feedback signal (fbCLK_in) through the first and thesecond replica circuits 44 and 43, thereby correcting delay. As aresult, the DLL circuit 42 generates a third clock intCLK to have thesame phase with the feedback output signal. The first replica circuit 44for modeling transmission delay into the register and delay circuit unit40 and the memory devices 61, 62, 63 and 64 may be formed ofcombinations of common passive/active devices to adjust transmissiondelay, generally connected to the outside of chips. Preferably, thefirst replica circuit 44 may also be formed of command/addresstransmission line and termination circuit models to compensatedifferences in process/power voltage/temperature of PCB board. Inaddition, the second replica circuit for modeling transmission ofinternal output buffers may be preferably formed of output buffercircuit models in chips to compensate differences in process/powervoltage/ temperature of output buffers.

[0019] As discussed earlier, the disclosed memory system according tothe present invention may simplify the lay-out of semiconductor devicedesign because command/address clock signals are directly provided tomemory devices and there is no transmission lines for distributingcommand/address clock signals. The memory system may also prevent thecollision of clock domains by sampling command/address signals in memorydevices using write data capture clocks. Besides, the memory system mayreduce the cost and improve the jitter performance because it does notrequire separate PLL or DLL circuits, and prevent the degradation oftiming margins of system due to differences in a number of compensationcapacitors. Additionally, the present invention may provide a preferredembodiment which reduces the cost due to unification of register chipand PLL chip.

[0020] While the invention is susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and described in detail herein. However, itshould be understood that the invention is not limited to the particularforms disclosed. Rather, the invention covers all modifications,equivalents, and alternatives falling within the sprit and scope of theinvention as defined in the appended claims.

What is claimed is:
 1. A memory system comprising a plurality of memorydevices, including: a controller for outputting a first clock signal, asecond clock signal and a plurality of command/address input signalscorresponding to the plurality of memory devices, respectively: and aregister and delay circuit unit for outputting command/address outputsignals after receiving the command/address input signals from thecontroller and then correcting transmission delay due to transmissionlines; wherein the plurality of memory devices receive thecommand/address output signals from the register and delay circuit unitvia the transmission lines, respectively, and sample the command/addressoutput signals using the first clock signal directly inputted from thecontroller.
 2. The memory system according to claim 1, wherein theregister and delay circuit unit includes: a clock control circuit foroutputting a third clock signal after receiving the second clock signalfrom the controller and correcting transmission delay due to thetransmission lines; and a regist unit for outputting the command/addressoutput signal after buffering the command/address input signals of thecontroller and sampling the command/address input signals using thethird clock signal.
 3. The memory system according to claim 2, whereinthe clock control circuit and the regist unit are embodied into a singlechip.
 4. The memory system according to claims 2 or 3, wherein the clockcontrol circuit comprises: a DLL circuit; and a first replica circuitfor modeling transmission delay due to the transmission lines; whereinthe DLL circuit adjusts the third clock signal to have the same phase asthe second clock signal, and outputs the third clock signals of whichtransmission delay due to transmission line is corrected.
 5. The memorysystem according to claim 4, wherein the first replica circuit is formedfrom the group consisting of PCB line model, active device, passivedevice and combinations thereof.
 6. The memory system according to claim2, wherein the clock control outputs the third clock signal afterreceiving the second clock signal from the controller and correctingtransmission delay due to the transmission lines and transmission delayfrom the regist unit.
 7. The memory system according to claim 6, whereinthe clock control circuit and the regist unit are embodied into a singlechip.
 8. The memory system according to claims 6 or 7, wherein the clockcontrol circuit comprises: a DLL circuit; a first replica circuit formodeling transmission delay due to the transmission lines; and a secondreplica circuit for modeling transmission delay of the regist unit;wherein the DLL circuit adjusts the third clock signal to have the samephase as the second clock signal, and outputs the third clock signals ofwhich transmission delay due to transmission line is corrected includingtransmission delay of the regist unit.
 9. The memory system according toclaim 8, wherein the first and the second replica circuits are formedfrom the group consisting of PCB line model, passive device, activedevice and combinations thereof.
 10. The memory system according toclaim 1, wherein the transmission lines comprises global lines from theregister and delay circuit unit to branchpoint, branched from thebranchpoint and connected to a plurality of memory devices,respectively.
 11. The memory system according to claim 10, wherein amethod of connecting transmission lines from the register and delaycircuit unit to the plurality of memory devices is formed from the groupconsisting of daisy chain, hybrid T type and bifercate.
 12. The memorysystem according to claim 10, wherein the register and delay circuitunit comprises: a clock control circuit for outputting a third clocksignal after receiving a second clock signal from the controller andcorrecting transmission delay due to the global transmission lines; anda regist unit for outputting the command/address output signals afterbuffering the command/address input signals and sampling the third clocksignal.
 13. The memory system according to claim 12, wherein the clockcontrol circuit and the regist unit are embodied into a single chip. 14.The memory system according to claims 12 or 13, wherein the clockcontrol circuit comprises: a DLL circuit; and a first replica circuitfor modeling transmission delay due to the global transmission lines;wherein the DLL circuit adjusts the third clock signal to have the samephase as the second clock signal, and outputs the third clock signals ofwhich transmission delay due to the global transmission line iscorrected.
 15. The memory system according to claim 14, wherein thefirst replica circuit is formed from the group consisting of PCB linemodel, active device, passive device and combinations thereof.
 16. Thememory system according to claim 12, wherein the clock control circuitoutputs a third clock signal after receiving a second clock signal fromthe controller and correcting transmission delay due to the globaltransmission lines and transmission delay in the regist unit.
 17. Thememory system according to claim 16, wherein the clock control circuitand the regist unit are embodied into a single chip.
 18. The memorysystem according to claims 16 or 17, wherein the clock control circuitcomprises: a DLL circuit; a first replica circuit for modelingtransmission delay due to the global transmission line; and a secondreplica circuit for modeling transmission delay in the regist unit;wherein the DLL circuit adjusts the third clock signal to have the samephase as the second clock signal, and outputs the third clock signals ofwhich transmission delay due to the global transmission line iscorrected including transmission delay of the regist unit.
 19. Thememory system according to claim 18, wherein the first and the secondreplica circuits are formed from the group consisting of PCB line model,active device, passive device and combinations thereof.